The design of static or dynamic, ratioed linear FET circuitry follows three conventional steps. First, the selection of a maximum allowable power distribution is made for the design, given the thermal limits of the technology and the application. Secondly, the nominal load device dimensions are selected such that the power defined in the first step will not be exceeded despite variations in process parameters such as threshold, transconductance, or topological variation. In addition, variations in environmental parameters such as power supply voltages or temperatures must be taken into consideration, with the wider variations in parameters requiring a smaller permissible nominal power in the load device and the consequent slower performance for the circuit. Thirdly, the minimum active device dimensions are selected such that the circuit exhibits acceptable voltage gain and noise immunity despite worst case parameter variations. Larger parameter variations lead to larger active devices which in turn present increased loading to the circuits that drive them, thereby slowing wave form propagation in the circuit. After these three steps in the design of ratioed linear load FED circuitry have been executed, all degrees of freedom have been specified. Although the circuit's nominal performance is completely determined, the circuit's worst case performance will be slower than that nominal performance by an amount that increases with the tolerance in the process and environmental parameters. Thus, the resulting circuit design may only be used in those applications that can tolerate this worst case performance.
Variations in process and environmental parameters degrade the design by increasing the maximum power dissipation of the circuit, by requiring an increased size in the devices to maintain the desired gain, and by increasing the ratio of worst case to nominal performance of a circuit designed to these power and gain constraints.
Attempts have been made in the prior art to compensate for variations in process parameters on a LSI chip, an example of which is the Pleshko, et al. U.S. Pat. No. 3,609,414 filed Aug. 20,, 1968 and assigned to the instant assignee. Pleshko discloses an on-chip circuit for compensating for variations in the process parameters by compensating for the resulting threshold voltage variation in FET devices embodied in the chip by controlling the substrate voltage of the chip. Although the Pleshko, et al. invention works well for its particular application, it has the disadvantage of imposing the compensation on every circuit on the chip, thereby precluding the selective compensation of multiple threshold circuits such as enhance/deplete FET circuitry. An additional problem with the Pleshko, et al. compensation technique is that in an N-channel device compensated by substrate voltage control, high threshold voltages would be compensated by low substrate bias voltages. Low substrate bias voltages increase the junction capacitance which further degrades performance of the circuits. Also, low substrate bias voltages may increase the probability of parasitics formed by surface inversion at low substrate bias.